Introduction to ASIC Design Flow
Any IC other than a general purpose IC which contain the functionality of thousands of gates is usually called an ASIC (Application Specific Integrated Circuit). ASICs are designed to fit a certain application. An ASIC is a digital or mixed-signal circuit designed to meet specifications set by a specific project. The basic ASIC Design Flow is Shown in.
ASIC Design Flow
EDA Tool Flow for ASIC Design
The EDA Tool that is used for synthesis of a RTL code to GDS II format is Magma Blast Fusion. The details of the Magma Design Flow is explained below.
Introduction Magma ASIC Design Flow:
Blast Plan Pro is used for the hierarchical design of large integrated circuits (ICs) and systems-on-chip (SoCs) with Magma's production-proven RTL-to-GDSII flow. Hierarchical design methodologies are typically adopted to handle very large designs or to support the concurrent design of a complex chip by a design team. Blast Plan Pro meets both of these requirements and delivers the additional benefit of predictable design closure.
The Magma tools form an integrated set of design engines that are combined with a Tcl interpreter and a sophisticated graphical user interface (GUI). These tools are software applications developed and distributed by Magma Design Automation Incorporated.
The typical simplified design flow of the Magma Blast Fusion is shown in the below.
This tutorial describes how to use the Magma Blast Fusion using command prompt to run these steps on a provided design. Follow the instructions provided in this tutorial to create scripts that perform the steps for the provided design.
The following Figure 4 shows the structure of this tutorial. The instructions for importing the design and constraints depend on whether you start from a netlist or from RTL. After you import the design and constraints, the remaining flow steps are the same.
These instructions use only the options applicable to the provided design, but the other options in the command prompt are operational. The Magma tool flow supports design entry using the GUI mode and Text mode. The RTL to GDSII flow is explained using a sequential circuit.
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